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Silicon Explorer Specifications
Aliasing - The condition that occurs when data from the target system is sampled at a rate slower than the
rate at which data changes. When this happens, meaningless data is displayed because the analyzer
misses the changes in data that occurred between sample points.
ASCII - stands for American Standard Code for Information Interchange. ASCII is an eight bit numeric code
that represents text characters.
Asynchronous Acquisition - An acquisition that is made using a clock signal generated internally by the
analyzer. This clock is unrelated to the clock in the target system, and can be set by the user.
B
Bus - See Channel Bus
C
Channel - An input signal line used by the logic analyzer to acquire data.
Channel Bus - A user-defined group of input channels whose combined numeric value is displayed in a
user specified radix .
Clock - The regular signal pulse that determines the sampling rate for the logic analyzer. See also
acquisition clock , external clock , and internal clock .
Clock Qualifier - An external signal that acts as a gate for the acquisition clock. When the external signal is
false, the acquisition clock is not allowed to load acquired data into acquisition memory.
The Clock Qualifier is handy when we only want to observe signal activity taking place when a particular
chip is selected. For example, if the system under test has three devices of the same type connected to a
common bus, one of which appears to be defective, we might want to record signal activity on the bus only
when the suspect device is selected.
If the logic analyzer's Clock Qualifier input were connected to the chip select line of the device we were
interested in, the analyzer would record data only when the chip's select line was active. The Clock Qualifier
allows us to filter out irrelevant data by only clocking data of interest into the sample buffer. See also
acquisition memory .
Collapse Bus - The process of returning a channel bus from its expanded view to its bus view. See expand
bus .
Condition - A value or event which the logic analyzer can recognize. A condition can be a transition on a
single channel, a combination of logic highs and lows across multiple channels, a certain number of clock
cycles, etc. See also pattern .
Cursor - A vertical line representing a specific location on the logic analyzer display.
D
Define Bus - The process of grouping a set of related signals together as a single, composite signal whose
value is the numeric combination of signals it contains. See undefine bus .
Don't Care - A symbol indicating that the channel(s) associated with the symbol may be any logic logic
value and the trigger, find or highlight pattern will still match. (see find , highlight , and trigger )
Download - The process of transferring acquisition memory contents from the Pod to the host computer.
E
Edge - A signal transition from low to high or from high to low.
Edge Triggering - The method of triggering on a low-to-high or high-to-low transition instead of on a low or
high voltage threshold.
Expand Bus - The process of displaying the individual signal which make up a bus, without undefining the
group. See collapse bus .
External Clock - A clock signal external to the logic analyzer and usually synchronous with the system
under test. See also acquisition clock and internal clock .
External Clocking - A clock mode in which the sampling of the input signals is synchronous with the
external clock signal.
F
Find Pattern - A pattern used to locate a specific data pattern within acquisition memory.
G, H
Silicon Explorer II User's Guide
63
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